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| IPB03N03LA IPI03N03LA, IPP03N03LA OptiMOS(R)2 Power-Transistor Features * Ideal for high-frequency dc/dc converters * Qualified according to JEDEC for target applications * N-channel - Logic level * Excellent gate charge x R DS(on) product (FOM) * Very low on-resistance R DS(on) * Superior thermal resistance * 175 C operating temperature * dv /dt rated P-TO263-3-2 1) Product Summary V DS R DS(on),max (SMD version) ID 25 2.7 80 V m A P-TO262-3-1 P-TO220-3-1 Type IPB03N03LA IPI03N03LA IPP03N03LA Package P-TO263-3-2 P-TO262-3-1 P-TO220-3-1 Ordering Code Q67042-S4178 Q67042-S4180 Q67042-S4179 Marking 03N03LA 03N03LA 03N03LA Maximum ratings, at T j=25 C, unless otherwise specified Parameter Continuous drain current Symbol Conditions ID T C=25 C2) T C=100 C Pulsed drain current Avalanche energy, single pulse Reverse diode dv /dt Gate source voltage4) Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 1) Value 80 80 385 960 6 20 Unit A I D,pulse E AS dv /dt V GS P tot T j, T stg T C=25 C3) I D=80 A, R GS=25 I D=80 A, V DS=20 V, di /dt =200 A/s, T j,max=175 C mJ kV/s V W C T C=25 C 150 -55 ... 175 55/175/56 J-STD20 and JESD22 Rev. 1.4 page 1 2004-02-05 IPB03N03LA IPI03N03LA, IPP03N03LA Parameter Symbol Conditions min. Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm2 cooling area5) Electrical characteristics, at T j=25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=100 A V DS=25 V, V GS=0 V, T j=25 C V DS=25 V, V GS=0 V, T j=125 C Gate-source leakage current Drain-source on-state resistance I GSS R DS(on) V GS=20 V, V DS=0 V V GS=4.5 V, I D=55 A V GS=4.5 V, I D=55 A, SMD version V GS=10 V, I D=55 A V GS=10 V, I D=55 A, SMD version Gate resistance Transconductance RG g fs |V DS|>2|I D|R DS(on)max, I D=55 A 25 1.2 1.6 0.1 2 1 A V 1 62 40 K/W Values typ. max. Unit 56 10 10 3.6 3.3 2.5 2.2 0.9 112 100 100 4.4 4.1 3.0 2.7 S nA m 2) Current is limited by bondwire; with an R thJC=1 K/W the chip is able to carry 175 A. See figure 3 T j,max=150 C and duty cycle D <0.25 for V GS<-5 V 3) 4) 5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.4 page 2 2004-02-05 IPB03N03LA IPI03N03LA, IPP03N03LA Parameter Symbol Conditions min. Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics6) Gate to source charge Gate charge at threshold Gate to drain charge Switching charge Gate charge total Gate plateau voltage Gate charge total, sync. FET Output charge Reverse Diode Diode continous forward current Diode pulse current Diode forward voltage IS I S,pulse V SD T C=25 C V GS=0 V, I F=80 A, T j=25 C V R=15 V, I F=I S, di F/dt =400 A/s 0.96 80 385 1.2 V A Q gs Q g(th) Q gd Q sw Qg V plateau Q g(sync) Q oss V DS=0.1 V, V GS=0 to 5 V V DD=15 V, V GS=0 V V DD=15 V, I D=40 A, V GS=0 to 5 V 16 8.5 12 20 43 3.1 37 48 21 11.2 18 28 57 49 64 V nC nC C iss C oss Crss t d(on) tr t d(off) tf V DD=15 V, V GS=10 V, I D=20 A, R G=2.7 V GS=0 V, V DS=15 V, f =1 MHz 5283 2231 304 18 8.5 45 7.5 7027 2967 457 26 13 68 11 ns pF Values typ. max. Unit Reverse recovery charge Q rr - - 20 nC 6) See figure 16 for gate charge parameter definition Rev. 1.4 page 3 2004-02-05 IPB03N03LA IPI03N03LA, IPP03N03LA 1 Power dissipation P tot=f(T C) 2 Drain current I D=f(T C); V GS10 V 160 140 100 80 120 100 60 P tot [W] 80 60 40 I D [A] 40 20 0 0 50 100 150 200 0 50 100 150 200 20 0 T C [C] T C [C] 3 Safe operation area I D=f(V DS); T C=25 C; D =0 parameter: t p 1000 1 s limited by on-state resistance 4 Max. transient thermal impedance Z thJC=f(t p) parameter: D =t p/T 10 10 s 1 100 s 100 0.5 I D [A] 1 ms Z thJC [K/W] DC 0.2 0.1 0.1 0.05 0.02 0.01 single pulse 10 ms 10 0.01 1 0.1 1 10 100 0.001 0 -6 10 10-5 0 10-4 0 -3 100 10 -2 0 10-10 10 0 1 V DS [V] t p [s] Rev. 1.4 page 4 2004-02-05 IPB03N03LA IPI03N03LA, IPP03N03LA 5 Typ. output characteristics I D=f(V DS); T j=25 C parameter: V GS 160 10 V 4.5 V 4.1 V 3.8 V 6 Typ. drain-source on resistance R DS(on)=f(I D); T j=25 C parameter: V GS 12 2.8 V 3V 3.2 V 3.5 V 3.8 V 140 120 10 8 I D [A] 3.5 V R DS(on) [m] 100 80 60 3.2 V 6 4.1 V 4 4.5 V 40 3V 10 V 2 20 0 0 1 2 2.8 V 0 3 0 20 40 60 80 100 120 140 160 V DS [V] I D [A] 7 Typ. transfer characteristics I D=f(V GS); |V DS|>2|I D|R DS(on)max parameter: T j 160 140 120 8 Typ. forward transconductance g fs=f(I D); T j=25 C 140 120 100 100 80 60 40 175 C g fs [S] 25 C I D [A] 80 60 40 20 0 0 1 2 3 20 0 4 5 0 20 40 60 80 V GS [V] I D [A] Rev. 1.4 page 5 2004-02-05 IPB03N03LA IPI03N03LA, IPP03N03LA 9 Drain-source on-state resistance R DS(on)=f(T j); I D=55 A; V GS=10 V 10 Typ. gate threshold voltage V GS(th)=f(T j); V GS=V DS parameter: I D 6 2.5 5 2 4 1000 A 98 % R DS(on) [m] V GS(th) [V] 1.5 100 A 3 typ 1 2 1 0.5 0 -60 -20 20 60 100 140 180 0 -60 -20 20 60 100 140 180 T j [C] T j [C] 11 Typ. Capacitances C =f(V DS); V GS=0 V; f =1 MHz 12 Forward characteristics of reverse diode I F=f(V SD) parameter: T j 10000 Ciss 1000 25 C 175 C 175 C, 98 % Coss 100 25 C, 98 % C [pF] 1000 I F [A] 10 Crss 100 0 5 10 15 20 25 30 1 0 0.5 1 1.5 2 V DS [V] V SD [V] Rev. 1.4 page 6 2004-02-05 IPB03N03LA IPI03N03LA, IPP03N03LA 13 Avalanche characteristics I AS=f(t AV); R GS=25 parameter: T j(start) 100 25 C 150 C 100 C 14 Typ. gate charge V GS=f(Q gate); I D=40 A pulsed parameter: V DD 12 10 5V 15 V 20 V 8 10 V GS [V] 1 10 100 1000 I AV [A] 6 4 2 1 0 0 20 40 60 80 100 t AV [s] Q gate [nC] 15 Drain-source breakdown voltage V BR(DSS)=f(T j); I D=1 mA 16 Gate charge waveforms 29 V GS 28 27 26 Qg V BR(DSS) [V] 25 24 23 22 21 20 -60 -20 20 60 100 140 180 V g s(th) Q g (th) Q gs Q sw Q gd Q gate T j [C] Rev. 1.4 page 7 2004-02-05 IPB03N03LA IPI03N03LA, IPP03N03LA Package Outline P-TO263-3-2: Outline Footprint Packaging Dimensions in mm Rev. 1.4 page 8 2004-02-05 IPB03N03LA IPI03N03LA, IPP03N03LA P-TO262-3-1: Outline P-TO220-3-1: Outline Packaging Dimensions in mm Rev. 1.4 page 9 2004-02-05 IPB03N03LA IPI03N03LA, IPP03N03LA Published by Infineon Technologies AG Bereich Kommunikation St.-Martin-Strae 53 D-81541 Munchen (c) Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts started herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices, please contact your nearest Infineon Technologies office in Germany or our Infineon Technologies representatives worldwide (see address list). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact your nearest Infineon Technologies office. Infineon Technologies' components may only be used in life-support devices or systems with the expressed written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.4 page 10 2004-02-05 |
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